Refereed Journal Articles
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P.-C. Lee†, M. Choi, D. Contreras Mora, A. Ross, S. Yun, D. Pal, D. Go, J. Dutta, X. Wang, M. Clark, L. Chen, R. Kanjolia, M. Moinpour, H. Chandra, S. Kumar, and A. C. Kummel*, “Quasi-Ballistic Thermal Transport in Vertically Aligned h-BN,” ACS Omega, vol. 11, no. 42, pp. 64801–64811, Oct. 2026. [Link]
Hexagonal boron nitride (h-BN) has attracted significant interest in the semiconductor industry due to its wide bandgap (5.95 eV), high anisotropic thermal conductivity, and low dielectric constant. However, the formation of crystalline h-BN conventionally requires high processing temperatures, which are incompatible with back-end-of-line (BEOL) integration and advanced packaging processes that must remain below 400 °C to avoid degradation of front-end devices. In this work, trichloroborazine (TCB) was systematically investigated using ammonia as the nitrogen co-reactant under both plasma-enhanced atomic layer deposition (PEALD) and atomic layer annealing (ALA) conditions. In the ALA process, low-energy inert ions are shown to enable in situ crystallization at temperatures well below those required for conventional MOCVD. As a result, highly ordered, vertically aligned polycrystalline h-BN films were deposited within a BEOL-compatible temperature window of 300–400 °C. The as-deposited ALA h-BN films exhibited clear signatures of cross-plane quasi-ballistic phonon transport over a thickness range of 20–50 nm, characterized by a thickness-independent effective thermal resistance of ∼6–9 m2 K GW–1. This invariance with film thickness indicates that phonon mean free paths exceed the film thickness, confirming quasi-ballistic heat transport enabled by the high crystallinity and preferential vertical alignment of the h-BN domains. -
S. Krishnakumar†, Y. Popryho, M. Choi, R. R. Khorasani, M. Swaminathan, S. Kumar, and I. Partin-Vaisband*, “A Comprehensive Design Framework for Vertical Power Delivery in High-Performance Computing,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 16, no. 9, pp. 2089–2102, Sep. 2026. [Link]
Power delivery—including high-to-low voltage conversion, complex power distribution across heterogeneously integrated chiplets, and efficient interconnect allocation—remains a critical bottleneck in high-performance computing (HPC) systems. Existing vertical power-delivery (VPD) solutions are estimated to achieve less than 70% system-wide end-to-end power-delivery efficiency, defined from platform input power to delivered on-chip load power, with substantial energy lost as heat before reaching on-chip point-of-loads (POLs). In the absence of systematic design methodologies, evaluating power quality, exploring architectural alternatives, and optimizing performance rely on computationally prohibitive simulations, resulting in suboptimal designs. This article introduces an end-to-end scalable power-delivery framework for HPC systems, including distributed VPD (DVPD) architecture, DVPD design optimization methodology, and analytical models. The framework leverages substrate-embedded GaN power switches together with arrays of unit inductors and capacitors tailored for HPC applications. Multistage power conversion schemes (48-to-1 V, 48-to-24-to-1 V, and 48-to-12-to-1 V) are explored, with system-wide voltage drops and power losses evaluated under steady-state conditions. Design specifications for passive and active devices are formulated to meet next-generation efficiency targets. For the 48-to-1 V case, the proposed DVPD approach achieves 84% system-wide efficiency while occupying 54% of the area beneath the load system, with efficiency increasing to 87.6% at 75% area utilization across a 1–50 kW load range. Furthermore, steady-state voltage drops peak at 2.7% and transient drops at 9% (without decoupling capacitors), demonstrating the viability of DVPD for future wafer-scale HPC platforms. -
M. Choi†, R. Dutta, P. Saha, M. Singh, S. Mukhopadhyay, S. Datta, and S. Kumar*, “Deep Operator Network-Accelerated Spatiotemporal Temperature Field Assessment of Fin Field-Effect Transistor Arrays,” Appl. Therm. Eng., vol. 304, pt. 1, Art. no. 132498, Sep. 2026. [Link]
In fin field-effect transistor (FinFET) arrays, evaluating spatiotemporal temperature distributions that account for thermal crosstalk across neighboring FinFETs is needed to understand hotspot formation, yet iterative quantification remains computationally demanding. This paper presents a deep operator network (DeepONet)-based surrogate modeling framework to enable fast and accurate spatiotemporal temperature assessment in FinFET arrays. First, size-dependent thermal conductivity is derived from density functional theory (DFT) to account for phonon-boundary scattering within the fin nanostructures. Transient temperature fields are subsequently generated using a finite volume method (FVM) solver, with power dissipation profiles from calibrated technology computer-aided design (TCAD) simulations. The DeepONet is then trained on these datasets to recursively map current temperature and power profiles to the temperature distribution at the next time step. Once trained, the surrogate model achieves a computational speedup of approximately 2500 times compared to the FVM solver in predicting one 3.5 ns transient temperature response for a given power dissipation profile, while maintaining high prediction accuracy, with over 92% of nodal errors falling below 3 K, thereby enabling rapid thermal screening of FinFET arrays. -
M. Choi†, S. Krishnakumar, Y. Popryho, R. R. Khorasani, M. Swaminathan, I. Partin-Vaisband, and S. Kumar*, “Self-Consistent Electrothermal Modeling of Distributed Vertical Power Delivery Architecture with Substrate-Embedded Microfluidic Cooling,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 16, no. 7, pp. 1534–1542, Jul. 2026. [Link]
Lateral power delivery (LPD) becomes infeasible for high-performance computing (HPC) processors operating at voltages near 1 V with current densities of 2 A·mm−2 due to large routing losses and Joule heating. Distributed vertical power delivery (DVPD) with integrated voltage regulators (IVRs) addresses this challenge by placing conversion stages close to the load, while substrate-embedded microfluidic cooling provides effective heat-dissipation pathways for inner tiers in vertically dense stacks. However, frameworks for self-consistent electrothermal modeling of DVPD at the system scale remain underexplored. This work develops such a framework, achieving high physical fidelity and computational efficiency. These attributes are realized by enforcing geometric and power profile consistency between the electrical and thermal models and through automation and optimized meshing. Applied to a 48-to-1 V DVPD architecture delivering 1 kW to a 500 mm2 die at 2 A·mm−2, the framework yields a self-consistent solution near the 85 °C threshold with a total system loss of 231 W and a maximum temperature of 85.7 °C, requiring a mass flow rate of 1.39 g·s−1 in embedded microchannels. Compared to an uncoupled initial estimate of 200 W with an initial mass flow rate of 1 g·s−1, the total system loss increases by about 15.8 %, which shows that neglecting electrothermal coupling underestimates both losses and cooling requirements. Additionally, region-specific meshing balances mesh resolution by refining near critical features and coarsening elsewhere, reducing both meshing and per-iteration times by over 30.0 % without loss of prediction accuracy. -
D. Go†, V. Ashita, A. Wang, M. Choi, H. S. Song, S. Yun, D. Pal, P.-C. Lee, J. Dutta, J. Ryu, S. Kumar, C. V. Thompson, M. S. Bakir, and A. C. Kummel*, “Chiplet Encapsulation and Planarization with 100 μm Deep Gaps using AlN Powder Spray + Sputter Hybrid Deposition,” Adv. Eng. Mater., vol. 28, no. 6, Art. no. e202502821, Mar. 2026. [Link]
This study presents a hybrid chiplet encapsulation structure that integrates aerosol-deposited (AD) and sputtered aluminum nitride (AlN) films to address thermal and mechanical challenges in advanced packaging. AD AlN rapidly fills high-aspect-ratio trenches (100 μm deep, 10 μm wide) at room temperature and provides an excellent coefficient of thermal expansion similar to silicon. After conformal filling, the overburden AD AlN is removed by mechanical polishing, enabling subsequent deposition of sputtered AlN for enhanced vertical heat dissipation. A 1.7 μm-thick sputtered AlN film exhibited high thermal conductivity of 113 (+26.8/–21.5) W/(m*K), as measured by frequency-domain thermoreflectance. A copper buffer layer was inserted between the silicon substrate and AD AlN to absorb impact stress during deposition, which effectively protected the substrate as confirmed by transmission electron microscopy-energy dispersive X-ray spectroscopy (TEM-EDS) analysis. Scanning electron microscopy imaging revealed void-free trench filling and smooth surface morphology. Warpage analysis identified overburden AD AlN as the main source of compressive stress, while the in-trench and sputtered AlN layers had minimal impact. This dual-deposition approach leverages the advantages of both methods—AD for rapid trench filling and sputtering for thermal performance—offering a scalable, thermally efficient, and mechanically robust solution for next-generation electronic packaging. -
S. Yun†, D. Go, M. Choi, R. Kondakindi, P.-C. Lee, P. R. Bandaru, S. Kumar, and A. C. Kummel*, “High Speed, High Thermal-Conductivity of Aluminum Nitride Deposited by DC Reactive Sputtering at Low Temperature in the Transition Regime,” Ceram. Int., vol. 52, no. 4, pp. 4777–4786, Feb. 2026. [Link]
Near-room-temperature high-speed sputter deposition is crucial in thermal management semiconductor applications due to its compatibility with packaging, back-end-of-line (BEOL) applications, and strain minimization due to coefficient of thermal expansion mismatch between the film and substrate. This study documents a record thermal conductivity for AlN films deposited near room temperature, ∼96 W/m·K for 1.2 μm thick AlN deposited at high speed (30 nm/min). The key factors in enhancing thermal conductivity are: (i) operation of the sputter target in the transition regime, (ii) precise control of sample bias (ranging from 0 V (GND) to −50 V), and (iii) high sputter power density (up to 400 W which equates to 20 W/cm2). The high ion flux enable by operation in the transition regime (target weakly nitrided) and optimal ion energy induce a high deposition rate of single-texture grains in the AlN films while minimizing substrate damage and oxygen contamination. AlN sputter deposition under transition mode is essential for obtaining high-speed deposition (30 nm/min) while maintaining high crystal quality as shown by an XRD a FWHM of 2.3° and an AFM RMS roughness of 1.5 nm. Two distinct methods for analyzing thermal conductivity applied to over 20 different AlN films produced comparable values, emphasizing the potential of AlN films as effective heat spreaders. -
P.-C. Lee†, M. Choi, D. Contreras Mora, K. Wang, S. Yun, D. Go, J. Dutta, D. Pal, S. Kumar, and A. C. Kummel*, “High-Speed AlN Film Deposition via Low-Pressure Bipolar High Power Impulsed Magnetron Sputter for Enhanced Thermal Conductivity,” Thin Solid Films, vol. 832, Art. no. 140821, Dec. 2025. [Link]
Reactive high power impulse magnetron sputtering (R-HiPIMS) plus kick is a bipolar sputtering technique that enhances the ionization of sputtered atoms and allows precise control of ion energy by a positive kick voltage pulse at the end of negative pulse on the target side [1]. The energetic ions generated by R-HiPIMS enable the transition of film structure from amorphous to crystalline at even room temperature. In the present study, the stability of low-pressure HiPIMS (High power impulse magnetron sputtering) plus kick plasma has been investigated, with frequency identified as a crucial factor in maintaining the plasma at low Ar background pressure. For AlN deposition, the impacts of various parameters, including positive pulse width and positive voltage, have been examined. A record-high deposition rate of 60 nm/min for AlN was achieved, corresponding to a standardized rate of 0.18 nm/W*min; this is consistent with the low-pressure HiPIMS plus kick, which maintains the target in a partially nitrided state. For deposition at 120 °C, X-ray diffraction analysis revealed a monotonic decrease in the full width at half maximum of rocking curves as film thickness increased, consistent with Transmission Electron Microscopy imaging showing coherent grain boundaries even on thick films. Among the two low-pressure HiPIMS plus kick samples examined, the highest thermal conductivity was 159.9 W/m·K (+16.7 / -18.5 W/m·K) at a thickness of around 1.5 μm, exhibiting strong industrial potential by achieving a high deposition rate while maintaining high thermal conductivity, low roughness, and low deposition temperature. -
M. Choi†, D. Vaca, and S. Kumar*, “Machine Learning-Enabled Fast and Accurate Inversion of Thermal Properties at the Micro- and Nanoscale via Optical Metrology,” Annu. Rev. Heat Transf., vol. 28, pp. 277–337, Oct. 2025. [Link]
Escalating power densities in monolithic three-dimensional (M3D) integrated circuits (ICs) and heterogeneous integration (HI) technologies intensify hot spots in upper tiers and dense interconnects, demanding precise, scale-aware thermal characterization to unlock effective thermal management strategies. Micro- and nanoscale optical metrologies, including frequency- and time-domain thermoreflectance (FDTR and TDTR), transient thermoreflectance (TTR), and laser-based Ångström method, meet this need by linking measured surface signals to subsurface properties through physics-based forward models. Yet the corresponding inverse problems present different mathematical hurdles. For example, FDTR, TDTR, and TTR inversions are nonlinear, so the least-squares fits can converge to local minima. In contrast, the Ångström inversion is linear, yet least-squares estimates are susceptible to noise-driven variance amplification. Such limitations have motivated machine learning (ML) approaches that deliver comparable or improved accuracy, enhance physical fidelity, and simultaneously accelerate inversion. For each optical metrology, this review formulates the forward and inverse problems, examines the limitations of conventional inversions, surveys ML inversion frameworks and benchmarks, and outlines open challenges and future research directions. -
M. Choi†, S. Krishnakumar, R. R. Khorasani, M. Swaminathan, I. Partin-Vaisband, and S. Kumar*, “Substrate-Embedded Microfluidic Cooling of Distributed Vertical Power Delivery Architectures for High-Performance Computing Processors,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 15, no. 9, pp. 1912–1920, Sep. 2025. [Link]
The advancement of high-performance computing (HPC) demands processors with higher transistor densities and current densities up to 2 A/mm2 , posing significant thermal management challenges. Traditional lateral power delivery (LPD) architectures are inadequate due to increased power distribution network (PDN) losses and space constraints. Distributed vertical power delivery (DVPD) architectures with integrated voltage regulators (IVRs) offer a promising solution but introduce substantial thermal issues, especially in 3-D stacked configurations where inner tiers have limited heat dissipation pathways. This article presents PyAEDT-automated numerical simulations of three 48-to-1-V DVPD architectures to investigate thermal behaviors in 3-D stacked designs, with and without substrate-embedded microchannels. The architectures differ in power switch configurations: 1) single-layer embedded gallium nitride (GaN) transistors; 2) dual-layer embedded GaN transistors; and 3) a combination of embedded and flip-chipped GaN transistors. Without microchannels, none of the architectures could maintain operational temperatures below the threshold of 85 ∘C , with maximum temperatures exceeding 145 ∘C . Incorporating parallel microchannels effectively reduces temperatures below the threshold, enabling 80% system-wide efficiency while supporting high current densities. The required pumping power for microchannel cooling was modest at appropriate flow rates, representing less than 0.1% of the processor’s power consumption. Utilizing PyAEDT automation reduced total simulation time by up to 95% in the studied architectures with microchannels. -
P.-C. Lee†, A. J. McLeod, M. Choi, D. Vaca, D. Contreras Mora, K. Wang, S. Yun, J. Dutta, D. Pal, S. Kumar, and A. C. Kummel*, “Achieving a High Thermally Conductive One Micron AlN Deposition by High Power Impulse Magnetron Sputtering Plus Kick,” ACS Appl. Mater. Interfaces, vol. 16, no. 20, pp. 26664–26673, May 2024. [Link]
High-power impulse magnetron sputtering (HiPIMS) plus kick is a physical vapor deposition method that employs bipolar microsecond-scale voltage pulsing to precisely control the ion energy during sputter deposition. HiPIMS plus kick for AlN deposition is difficult since nitride deposition is challenged by low surface diffusion and high susceptibility to ion damage. In this current study, a systematic examination of the process parameters of HiPIMS plus kick was conducted. Under optimized main negative pulsing conditions, this study documented that a 25 V positive kick biasing for AlN deposition is ideal for optimizing a high quality film, as shown by X-ray diffraction and transmission electron microscopy as well as optimal thermal conductivity while increasing high speed deposition (25 nm/min) and obtaining ultrasmooth surfaces (rms roughness = 0.5 nm). HiPIMS plus kick was employed to deposit a single-texture 1 μm AlN film with a 7.4° rocking curve, indicating well oriented grains, which correlated with high thermal conductivity (121 W/m·K). The data are consistent with the optimal kick voltage enabling enhanced surface diffusion due to ion-substrate collisions without damaging the AlN grains. -
M. Choi†, B. Goo, G. Cho, and S. J. Song*, “Swirl Enhancement Effect on Turbine Rim Seal Performance,” J. Turbomach., vol. 146, no. 5, Art. no. 051002, May 2024. [Link]
In gas turbines, sealing flow is extracted from the high-pressure compressor and supplied into the turbine wheel-space to suppress hot gas ingestion. Such hot gas ingestion is thought to be driven by the difference in either the static pressure or swirl between the mainstream and wheel-space flows. For the first time, experiments have been conducted in a low-speed single-stage axial turbine with a single-radial clearance rim seal and a “swirler” on the rotor disk. The objective is to evaluate the impact of enhanced wheel-space flow swirl on the rim seal performance. The swirler does not affect the mainstream flow. In the wheel-space, however, the swirler reduces static pressure; increases swirl; and improves rim seal performance (i.e., reduces the minimum sealing flowrate needed for hot gas ingestion prevention). Thus, the seal performance improvement occurs with increased difference in pressure and reduced difference in swirl between the mainstream and wheel-space flows. Therefore, it can be inferred that the rim seal performance depends more strongly on swirl than pressure. Preliminary gas turbine cycle performance studies indicate that net cycle efficiency benefits can be obtained.
Manuscripts Under Review
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M. Choi† and S. Kumar*, “STREAM 1.0: An Efficient Spatiotemporal Thermal Response Emulator Using Prescribed Velocity Fields for Advanced Microelectronics,” submitted for publication.
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M. Choi†* and S. Kumar*, “Rationally Enriched Chebyshev Trunk Bases for DeepONet Surrogates of High Péclet Entrance Transport,” submitted for publication.
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M. Choi†, M. Herndon, K. Uechi, N. Akel, and S. Kumar*, “Deep Operator Network Framework for Bidirectional Power-State and Temperature Analysis in Vertical Power Delivery Modules,” submitted for publication.
Refereed Conference Proceedings
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Best Paper News Release 1 · 2 · 3 · 4
M. Choi†, M. Herndon, K. Uechi, N. Akel, and S. Kumar*, “DeepONet-Enabled Fast and Scenario-Aware Spatial Temperature Prediction of a Vertical Power Delivery Module for Hyperscale Data Centers,” in Proc. 25th IEEE Intersoc. Conf. Therm. Thermomech. Phenom. Electron. Syst. (ITherm), Orlando, FL, USA, May 2026, accepted for publication.
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P.-C. Lee†, D. Contreras Mora, M. Choi, S. Yun, D. Pal, A. Ross, M. Clark, L. Chen, H. Chandra, R. Kanjolia, M. Moinpour, S. Kumar, and A. Kummel*, “Vertical aligned Hexagonal Boron Nitride with Ballistic Thermal Conductivity,” in Proc. Int. VLSI Symp. Technol. Syst. Appl. (VLSI TSA), Hsinchu, Taiwan, Apr. 2026. [Link]
Hexagonal boron nitride (h-BN) is attractive for BEOL integration due to its wide bandgap, low dielectric constant, and high intrinsic thermal conductivity; however, achieving crystalline BN below 400 °C remains challenging. We demonstrate a 350 °C atomic layer annealing ALD (ALA-ALD) process using BBDMAB and −25 V Ar+ substrate bias plasma to form vertically aligned, impurity-free h-BN. The ion-assisted crystallization reorients BN from layered to columnar domains, enabling ballistic phonon transport in sub-60 nm films. The resulting films an effective thermal boundary conductance of 149 MW m−2 K−1, a five-fold improvement over PEALD BN. This process provides a scalable pathway for nanoscale heat-spreading applications. -
R. Dutta†, M. Shon, S. Lim, P. Saha, M. Choi, M. P. Singh, S. Kumar, S. Mukhopadhyay, S. K. Lim, S. Yu, and S. Datta*, “Self-Heating in GAA Nanosheet FETs with integrated Back Side Power Delivery Network: Device to Circuit Electro-Thermal Analysis and Implications,” in Proc. IEEE Int. Reliab. Phys. Symp. (IRPS), Tucson, AZ, USA, Mar. 2026. [Link]
This work presents an electrothermal analysis of Gate-All-Around (GAA) Nanosheet (NS) FETs to reveal that, while Backside Power Delivery Network (BSPDN) provides logic density scaling advantages, it introduces thermal bottlenecks due to substrate thinning and the thermal insulation of backside dielectrics. These structural constraints impede heat dissipation, leading to junction temperature increases, such as a ΔTj of ∼150K at Vdd=0.7V, which escalates to over 300 K under the worst condition of VDd=1.3V. Such a strong self-heating effect results in a direct performance penalty, evidenced by over 10% frequency degradation in inverter-chain ring oscillators. These findings are critical for high-performance computing (HPC) systems that rely on voltage overdrive and overclocking, as the localized thermal congestion at the nanosheet level can effectively neutralize the throughput gain at advanced node. Our insights underscore the importance of thermal-aware device-circuit cooptimization to successfully navigate the thermal limitations inherent in next-generation logic architecture. -
Best Paper News Release 1 · 2
M. Choi†, S. Krishnakumar, Y. Popryho, R. R. Khorasani, M. Swaminathan, I. Partin-Vaisband, and S. Kumar*, “Automated Electro-Thermal Modeling Framework of Distributed Vertical Power Delivery Architectures with Substrate-Embedded Microfluidic Cooling,” in Proc. 24th IEEE Intersoc. Conf. Therm. Thermomech. Phenom. Electron. Syst. (ITherm), Dallas, TX, USA, May 2025. [Link]
Next-generation high-performance computing (HPC) systems require power delivery solutions capable of sustaining beyond 1 kW per monolithic chip, with current densities expected to reach or exceed 2 A/mm2. Distributed vertical power delivery (DVPD) architectures with integrated voltage regulators (IVRs) address this challenge by placing conversion stages closer to the processor, thereby reducing conduction losses. However, the interplay between temperature-dependent power dissipation and substrateembedded microfluidic cooling-particularly in 3D-stacked configurations where inner tiers have limited heat dissipation pathways-has been underexplored. This paper presents a PyAEDT-driven, automated electro-thermal modeling framework for 48 -to- 1 V DVPD architectures to accurately capture realistic power losses and pumping demands. Results demonstrate that ignoring electro-thermal feedback leads to significant underestimation of both power loss and IVR area. An electrical-only analysis predicts a total converter loss of 251.86 W, whereas integrating thermal effects raises this value to 285.91 W -an increase of about 13.5%. Likewise, IVR sizing grows by approximately 11% to mitigate elevated on-resistance and switching losses at higher temperatures. To maintain hot-spot temperatures below 85∘C, the required microfluidic flow rate must rise from 1 g/s, which is needed without considering electro-thermal interactions, to 2.47 g/s, generating a pressure drop of 47.9 kPa. Despite this higher flow rate, the pumping overhead remains only 122.32 mW, which is negligible compared to the extensive conduction and switching losses that would occur in inadequately cooled systems. -
M. Choi†, R. Dutta, P. Saha, M. P. Singh, S. Mukhopadhyay, S. Datta, and S. Kumar*, “Fast Prediction of Spatio-Temporal Temperature Profiles in FinFET Arrays via Numerical and Machine-Learning Approaches,” in Proc. IEEE Int. Electron Devices Meet. (IEDM), San Francisco, CA, USA, Dec. 2024. [Link]
Quantifying the spatio-temporal thermal response in FinFET arrays is crucial due to the detrimental impact of the self-heating effect (SHE) on reliability. However, thermal models which are computationally efficient and which can predict temperature at high spatio-temporal resolution are rare. This paper presents a highly efficient, three-dimensional (3D) multi-scale time-dependent temperature prediction model for 14 nm node bulk FinFET arrays, considering nanoscale thermal resistances and cross-coupling among FinFETs. First, a device-level electro-thermal model was developed using Synopsys Sentaurus TCAD to predict power dissipation and steady-state temperature profiles of a single FinFET and to characterize scattering parameters (S-parameters). Subsequently, a device-and array-level thermal model was constructed using Ansys Fluent to generate transient temperature maps, utilizing power dissipation profiles from the TCAD model. Finally, a machine learning (ML)-accelerated multi-scale thermal model was developed, enabling transient temperature maps to be predicted −2300 timesfaster than traditional Fluent simulations. -
Y. Im†, J. Kim, M. Choi, M. Bouzidi, X. Li, J. W. Kim, A. M. Muslu, S. Kumar, M. Swaminathan, S. K. Sitaraman, and Y. Joshi*, “Parametric Thermal Design for Heterogeneously Integrated High-Power Packages,” in Proc. ASME 2024 Int. Tech. Conf. Exhib. Packag. Integr. Electron. Photonic Microsyst. (InterPACK), San Jose, CA, USA, Oct. 2024. [Link]
As power densities increase in heterogeneously integrated systems, with the introduction of new 3D architectures and the increasing number of transistors on chips, there exists a continued bottleneck for thermal management. High temperatures have a drastic impact on memory performances and refresh cycles. Moreover, thermal coupling between neighboring chiplets on a package is increasing as the types of chips on a heterogeneously integrated package diversify, and this, in turn, creates different heat flux densities within a heterogeneously integrated package. Thus, there arises a need for the implementation of efficient thermal design and solutions that cater to high heat fluxes within a package as well as different heights for different chip stacks within a package. In this paper, we present a parametric thermal design of heterogeneously integrated packages for high-performance computing. We focus on a 2.5D packaging structure, which includes components including artificial intelligence (AI) accelerators and high bandwidth memory (HBM) on a silicon interposer. Analytically and numerically, we investigate the thermal challenges stemming from high power density in stacked dies, variations in die heights, and cooling limitations at the package surface. To mitigate temperature gradients within the package, we propose a thermal-aware package structure, emphasizing the inside architecture. Also, the thermal coupling effect is studied for multiple cooling technologies on the outer surface using a thermal violation region graph. This research has shown that not only the internal structure of the package but also its ability to transfer heat to the outer surface has a significant impact on the thermal coupling effect. Using our approach, we can design package architecture systematically considering the external cooling environment in the early design stage. -
P.-C. Lee†, A. J. McLeod, M. Choi, D. Vaca, S. Kumar, and A. C. Kummel*, “Thermal Conductivity Study of One Micron AlN Deposition by Bipolar High Power Impulse Magnetron Sputtering,” in Proc. IEEE Int. Interconnect Technol. Conf. (IITC), San Jose, CA, USA, Jun. 2024. [Link]
High Power Impulse Magnetron Sputtering (HIPIMS) has emerged as a promising technique for the deposition of thin films with superior properties. In this study, HIPIMS was combined with a positive target bias (Kick voltage) process to enhance AlN film quality further. Aluminum Nitride (AlN) thin films were deposited using this method and characterized using Transmission Electron Microscopy (TEM) and X-Ray Diffraction (XRD). The thermal properties of the films were investigated using Frequency Domain Thermoreflectance (FDTR). The results show that the HIPIMS plus Kick process significantly improves the film quality, leading to enhanced thermal conductivity (112 W/m·K) compared to conventional techniques. This work demonstrates the potential of HIPIMS in producing high-quality thin films with improved thermal properties, making it suitable for various applications in electronics and thermal management. -
S. Krishnakumar†, M. Choi, R. R. Khorasani, R. Sharma, M. Swaminathan, S. Kumar, and I. Partin-Vaisband*, “Vertical Power Delivery for High Performance Computing Systems with Buck-Derived Regulators,” in Proc. IEEE 74th Electron. Compon. Technol. Conf. (ECTC), Denver, CO, USA, May 2024. [Link]
With traditional power delivery architectures in state-of-the-art high-power (>1 kW) high-current density systems (>1 A/mm2), over 30% of the system-wide power is dissipated within the power delivery system, i.e., during the delivery of power from a printed circuit board (PCB) to functional die(s). Historically, in high-power systems, efficient low-power density voltage regulators have been placed on PCB, to minimize the conversion loss and advanced low-resistance interconnect technologies have been utilized to reduce the lateral routing loss in packaging power distribution network (PPDN). While power loss is reduced linearly with lower PPDN resistance, current reduction is desired due to the quadratic dependence of power on current. To efficiently deliver current from PCB to functional die, distributed vertical power delivery (DVPD) is preferred in this work. With this approach, power is delivered horizontally at high-voltage low-current and converted to low-voltage high-current close to functional die, near points-of-load (POLs), with optimal number of compact, power-efficient distributed on/in-interposer voltage regulators (VRs). Thus, lateral distribution of VRs is promising for mitigating conduction loss in both the VRs and horizontal packaging interconnect components. To increase the conversion efficiency and current density, an advanced network of parallel-connected vertically-stacked inductors and Gallium Nitride (GaN) power devices are considered. Analytical loss models and model-guided design methodology for optimizing the PCB-to-POL loss in a DVPD system are proposed in this work. A preferred power architecture for delivering 1-kW power to a functional 500-mm2 die is determined based on the proposed models and methodology, exhibiting system-wide efficiency of 85.6% and power density of 2 W/mm2. -
M. Choi†, S. Krishnakumar, R. R. Khorasani, I. Partin-Vaisband, R. Sharma, M. Swaminathan, and S. Kumar*, “Thermal Analysis of High Current Vertical Power Delivery Network with Embedded Microchannel Cooling,” in Proc. 23rd IEEE Intersoc. Conf. Therm. Thermomech. Phenom. Electron. Syst. (ITherm), Aurora, CO, USA, May 2024. [Link]
Advancements in high-performance computing (HPC) demand densified interconnect and assembly methods in power delivery networks (PDN). A challenge accordingly emerges with system-on-package (SoP) solutions using vertical power delivery networks (VPDNs), where heat dissipation from the die and the integrated voltage regulator (IVR) is a primary concern. This paper presents a numerical thermal analysis of two VPDN designs: distributed on- and in-interposer dual-phase multi-inductor hybrid (DPMIH) converters. Positioned vertically beneath the die for a 12 V-to-1 V single-stage, high-current power conversion using gallium nitride (GaN), these configurations are evaluated in scenarios with and without embedded microchannel cooling. With microchannel cooling, the analysis incorporates 103 microchannels, each 200 µm wide and 100 µm high, employing water as the working fluid. The aim is to maintain device temperatures below 90 °C during 1 kW power delivery to a monolithic 3D (M3D) die while minimizing pumping losses for microchannel cooling and ensuring total efficiency exceeds 80 % at a high current density. Numerical results show that without embedded microchannel cooling, the maximum system temperatures reach approximately 126.1 °C and 155.5 °C for on- and in-interposer configurations, respectively. Conversely, embedded microchannel cooling with a flow rate of 0.05 kg/s reduces maximum system temperatures to 54.6 °C and 74.6 °C for on- and in-interposer configurations, respectively. For maintaining temperatures just below the threshold of 90 °C, on-interposer conversion requires a flow rate over 0.015 kg/s, with pumping power consumption of at least 9.2 W, whereas in-interposer conversion demands a minimum flow rate of 0.025 kg/s, consuming 39.4 W of pumping power. -
S. Krishnakumar†, M. Choi, R. R. Khorasani, R. Sharma, M. Swaminathan, S. Kumar, and I. Partin-Vaisband*, “Design Considerations for DC-DC Voltage Regulators in Distributed Vertical Power Delivery Systems,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Singapore, May 2024. [Link]
Modern high performance integrated systems demand high-power (>1 kW) to be delivered at high current density (>2 A/mm2) from PCB to points-of-load (POLs) on-chip. Efficient delivery of high-quality power from PCB to POLs is a primary concern in modern high-power high-density integrated systems. With traditional power delivery approaches, high voltage is converted to high current on PCB, yielding prohibitively high power loss in horizontal packaging interconnect components. One approach to reduce this loss is with vertical power delivery (VPD), i.e., to deliver low current at high voltage horizontally and convert it to high current low voltage close to POLs. Voltage regulators (VRs) integrated within small footprint near POLs, however, exhibit high switching and inductor losses. As a result, state-of-the-art VPD systems still exhibit high IR voltage drops, power efficiency of less than 70%, and high thermal dissipation. Thus, the design of compact power efficient VRs is a primary concern with VPD approach. To enhance the overall performance of the PCB-to-POL power delivery system, distributed VPD is considered and architecture-specific design of VRs is investigated in this paper. The design methodology for determining optimal number and placement of VRs for a given power delivery architecture is also proposed. The approach has been demonstrated with on-interposer 12V/1V power converters, comprising Gallium Nitride (GaN) power devices and state-ofthe-art inductors and capacitors, yielding 85% power efficiency with 1-kA load at 2 A/mm2. -
P.-C. Lee†, A. J. McLeod, M. Choi, D. Vaca, D. Contreras Mora, S. Kumar, and A. C. Kummel*, “High Thermally Conductive, High-Speed Deposition of AlN by Bipolar High Power Impulse Magnetron Sputtering,” in Proc. Int. VLSI Symp. Technol. Syst. Appl. (VLSI TSA), Hsinchu, Taiwan, Apr. 2024. [Link]
In advanced 3D monolithic packaging practices, the gap filling between dielectric chips is typically performed by PECVD SiO2, which has a thermal conductivity of ∼1 W/m-K, hindering effective thermal management. Substituting SiO2 with polycrystalline AlN could result in more than a 100-fold enhancement in thermal conductivity while maintaining a relatively low leakage current. However, achieving this substitution requires a low-defect density, high-speed deposition of AlN at low temperatures (<400∘C). High-power impulse magnetron sputtering (HIPIMS) plus a reverse positive kick is a form of high-energy physical vapor deposition involving bipolar pulsing. In this study, single-texture 1-micron AIN film with a thermal conductivity of 121 W/m⋅K was successfully deposited with a growth rate of 25 nm/min using an advanced bipolar HIPIMS plus Kick pulse generator on a native oxide-free Si (111) substrate. The substantial plasma current (50 A at peak) and a slight reverse positive target bias (+25V) are applied to ensure that 90% of the Al and Ar atoms are ionized with the precise controlled energy, leading to the maximization of the material's capacity for heat dissipation as measured by frequency domain thermoreflectance (FDTR). -
M. Choi†, B. Goo, G. Cho, and S. J. Song*, “Swirl Enhancement Effect on Turbine Rim Seal Performance,” in Proc. ASME Turbo Expo 2023: Turbomach. Tech. Conf. Expo., Boston, MA, USA, Jun. 2023. [Link]
In gas turbines, sealing flow is extracted from the high-pressure compressor and supplied into the turbine wheel-space to suppress hot gas ingestion. Such hot gas ingestion is thought to be driven by the difference in either the static pressure or swirl between the mainstream and wheel-space flows. For the first time, experiments have been conducted in a low-speed single-stage axial turbine with a single-radial clearance rim seal and a “swirler” on the rotor disk. The objective is to evaluate the impact of enhanced wheel-space flow swirl on the rim seal performance. The swirler does not affect the mainstream flow. In the wheel-space, however, the swirler reduces static pressure; increases swirl; and improves rim seal performance (i.e., reduces the minimum sealing flow rate needed for hot gas ingestion prevention). Thus, the seal performance improvement occurs with increased difference in pressure and reduced difference in swirl between the mainstream and wheel-space flows. Therefore, it can be inferred that the rim seal performance depends more strongly on swirl than pressure. Preliminary gas turbine cycle performance studies indicate that net cycle efficiency benefits can be obtained.
Patents
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A. C. Kummel, P.-C. Lee, D. Contreras Mora, D. Go, S. Kumar, and M. Choi, “Aluminum Nitride Thin Film Deposition Using Sputtering,” U.S. Patent Appl. 20260110074A1, Apr. 23, 2026. [Link]
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M. Choi and S. J. Song, “Gas Turbine Engine with Improved Flow Stability and Cooling Efficiency,” Republic of Korea Patent 10-2206447, Jan. 18, 2021. [Link]
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M. Choi, S. J. Song, and B. Goo, “Gas Turbine Engine with Improved Sealing and Operability,” Republic of Korea Patent 10-2202368, Jan. 7, 2021. [Link]
Conference Presentations
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M. Singh†, M. Choi, L. Patra, R. Dutta, P. Saha, S. Mukhopadhyay, S. Datta, and S. Kumar*, “Machine Learning Enabled Fast and Accurate Thermal Model of Nanoscale Transistors and Circuits,” presented at the Gov. Microcircuit Appl. Crit. Technol. Conf. (GOMACTech) 2026, New Orleans, LA, USA, Mar. 9–12, 2026.
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P.-C. Lee†, D. Contreras Mora, M. Choi, S. Yun, D. Pal, A. Ross, M. Clark, L. Chen, R. Kanjolia, M. Moinpour, S. Kumar, and A. C. Kummel*, “Vertical Aligned Hexagonal Boron Nitride with High Interfacial Thermal Conductivity,” presented at the 56th IEEE Semicond. Interface Specialists Conf. (SISC), San Diego, CA, USA, Dec. 10–13, 2025.
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D. Contreras Mora†, P.-C. Lee, M. Choi, D. Go, S. Yun, M. Moinpour, L. Chen, M. Clark, R. Kanjolia, S. Kumar, and A. C. Kummel*, “Thermal Boundary Conductance of Ultrathin Aluminum Nitride Interfaces for Advanced Packaging,” presented at the 56th IEEE Semicond. Interface Specialists Conf. (SISC), San Diego, CA, USA, Dec. 10–13, 2025.
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D. Contreras Mora†, P.-C. Lee, M. Choi, S. Kumar, and A. C. Kummel*, “Low Pressure HiPIMS + Kick AlN Deposition with Ultra High Growth Rate,” presented at the Gov. Microcircuit Appl. Crit. Technol. Conf. (GOMACTech) 2025, Pasadena, CA, USA, Mar. 17–20, 2025.
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P.-C. Lee†, D. Contreras Mora, A. J. McLeod, M. Choi, D. Vaca, S. Kumar, and A. C. Kummel*, “Enhancing AlN Crystallographic Properties and Thermal Conductivity Using HiPIMS + Kick Deposition,” presented at the Gov. Microcircuit Appl. Crit. Technol. Conf. (GOMACTech) 2024, Charleston, SC, USA, Mar. 18–21, 2024.
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P.-C. Lee†, D. Contreras Mora, A. J. McLeod, M. Choi, D. Vaca, S. Kumar, and A. C. Kummel*, “Achieving a High Thermal Conductive One Micron AlN Deposition by High Power Impulse Magnetron Sputtering Plus Kick,” presented at the 54th IEEE Semicond. Interface Specialists Conf. (SISC), San Diego, CA, USA, Dec. 13–16, 2023.
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J. Pak†, S. Oh, and M. Choi*, “Computational Modeling for Investigating Flow Instabilities in Gas Turbine Rim Seals,” presented at the KSPE Spring Conf. 2020, Online via Zoom, Jul. 16–17, 2020.
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M. Choi†, B. Goo, and S. J. Song*, “Design of a Low-Speed Single-Stage Turbine Facility for Ingress Measurement,” presented at the IGTC 2019 Tokyo, Tokyo, Japan, Nov. 17–22, 2019.
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M. Choi†, B. Goo, and S. J. Song*, “Sealing Performance Measurement of Single Radial-Clearance Rim Seal,” presented at the KSFM Winter Conf. 2018, Yeosu, Republic of Korea, Nov. 28–30, 2018.
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M. Choi†, H. R. Kim, S. Kim, G. Cho, and S. J. Song*, “Measurement of Double-Clearance Rim Seal Performance to Prevent Hot Gas Ingestion in Large-Scale Gas Turbines,” presented at the KSFM Summer Conf. 2018, Jeju, Republic of Korea, Jul. 4–6, 2018.
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Best Presentation News Release
M. Choi†, G. Cho, and S. J. Song*, “Rebuilding of 1-Stage Axial Turbine Rim Seal Test Facility in Seoul National University,” presented at the KSFM Summer Conf. 2018, Jeju, Republic of Korea, Jul. 4–6, 2018.